1. Field of the Invention
The present invention relates generally to pulse generating circuits, and more particularly to such a pulse generating circuit incorporated into a microcomputer system so as to generate a pulse as an output signal of the system.
2. Description of the Prior Art
FIG. 8 is a block diagram showing an arrangement of a conventional pulse generating circuit such as disclosed in U.S. Pat. No. 4,805,199. In the illustration, numeral 1 represents a CPU, 2 designates a counter, 3 depicts a data bus, 4 denotes a clock generating circuit, 5 indicates a clock signal to be outputted from the clock generating circuit 4, and 6 is a comparison value register. Further, numeral 7 represents a digital comparator one input terminal of which is coupled to the counter 2 and the other input terminal of which is coupled to the comparison value register 6, 8 designates a counter buffer coupled to the counter 2, 8G depicts a gate for reloading the value of the counter buffer 8 to the counter 2 in accordance with an overflow signal of the counter 2, 9 denotes a clock switching circuit for performing a switching operation between an internal clock signal and an external clock signal, and 10 is a prescaler the input terminal of which is coupled to the clock switching circuit 9 and the output terminal of which is coupled to the counter 2. Still further, numeral 11 represents an external clock terminal coupled to one input terminal of the clock switching circuit 9, 12 designates a register buffer coupled to the comparison value register 6, 12G depicts a gate for loading the value of the register buffer 12 to the comparison value register 6 in accordance with the output signal of the digital comparator 7, 13 is a shift register where the internal data are shifted in accordance with the output signal of the digital comparator 7, and 14 denotes an output terminal coupled to the shift register 13.
Secondly, operation will be described hereinbelow with reference to FIG. 9. First, an initial value N.sub.1 is set to the counter 2, a reload value N.sub.2 to be reloaded by the overflow of the counter 2 is set to the counter buffer 8, time data M.sub.1 (&gt;N.sub.1) for outputting one edge of a pulse are written into the comparison value register 6, time data M.sub.2 (&gt;M.sub.1) for outputting the other edge of the output pulse are written into the register buffer 12, and data for the output pulse train are written into the shift register 13. Here, let it be assumed that the initial value of pulse output terminal 14 is taken to be "0".
As illustrated in FIG. 9, the counter 2 counts the clock input, divided by the prescaler 10, from the initial value N.sub.1 (time to). In response to the value of the counter 2 becoming equal to the value M.sub.1 of the comparison value register 6 at the time t.sub.1, the digital comparator 7 detects the coincidence therebetween to output a coincidence pulse, whereby the data of the shift register 13 is shifted by one bit. If "1" is set as the most significant bit after the shifting, "1" is outputted to the pulse output terminal 14. Further, at the same time, the coincidence pulse causes the data M.sub.2 within the register buffer 12 to be loaded in the comparison value register 6.
When due to the continuous counting operation of the counter 2 the counter value becomes equal to the value M.sub.2 of the comparison value register 6 at the time t.sub.2, the digital comparator 7 detects the coincidence therebetween so as to output a coincidence pulse, whereby the data of the shift register 13 is shifted by one bit. If the most significant bit after the shifting is "0", "0" is outputted to the pulse output terminal 14.
Further, assuming that due to the continuous counting operation of the counter 2 the overflow occurs at the time t.sub.4, the value N.sub.2 of the counter buffer 8 is loaded to the counter 2. In the case that values M.sub.3 (&gt;N.sub.2) and M.sub.4 (&gt;M.sub.3) are respectively written newly into the comparison value register 6 and the register buffer 12, pulse outputs appear at the pulse output terminal 14 at the times (times t.sub.5 and t.sub.6) when the counter values becomes equal to the values M.sub.3 and M.sub.4, respectively.
However, because of the above-described arrangement, there are problems arising with such a conventional pulse generating circuit in that one pulse generating circuit allows only one pulse output and hence, for outputting pulses to a plurality of output terminals, the circuit size becomes large to enlarge the chip size when incorporating it in an integrated circuit.